Network Vip

65nm FPGA employs permeating to many model’s wireless base stations for representatives’ high side

As TD-SCDMA enters the large-scale commercial experiment, WiMAX joins ITU and becomes the 4th 3G standard, Ericsson takes the lead in finishing LTE the whole chain to transmit and test at a high speed, IMT-Advanced motion at the beginning was collected, the situation that many standards coexist has appeared more and more in mobile communication. In reality often on a station location, there are many kinds of standard base stations such as air shower, CDMA, GSM, TD-SCDMA at the same time. How to reduce to research and develop the production cost, reduce and build, run, safeguard and upgrade the cost, common subject that become the apparatus manufacturer and the operator faces. As to this, base station the intersection of apparatus and manufacturer propose, face the whole the intersection of IP and many the intersection of mould and wireless base station, realize GSM, UMTS, CDMA, the intersection of WiMAX and many the intersection of module and large mode base stations, thus can realize the smooth gradual progress, from 3G standard after upgrading to HSDPA/HSUPA even LTE,etc. that 3G standards such as existing TD-SCDMA, WCDMA,etc. are smooth.

The FPGA programmable logic device of high performance, it is exactly one of the best construction platforms of many model’s wireless base stations. Xilinx takes the lead in 65nm platform FPGA where releasing and quantity has, have increased the lifespan of the systematic products and satisfied 3G effectively by a large amount of advanced technology and brand-new design, deal with the apparatus to the harsh requirement of the multi-function, performance, consumption and comprehensive cost in mobile communication standards such as LTE, IMT-Advanced,etc. and high performance.

High capacity, high performance

Though the clock frequency of work of DSP is brought GHz quantity grade up to, it is unable to meet the requirements for real-time character of the advanced application system. In other words, there is bad whereabouts all the time between the performance of algorithm complexity and traditional DSP. And, with issue of movement communication in future such as 3G, LTE, IMT-Advanced, the complexity straight line of real-time video compiled code algorithms such as wireless algorithms such as MIMO, OFDM, LDPC in the communication system,etc. and AVS,etc. rises, make this kind of drop keep further expanding.

Traditionally, this drop is dealt with the chip ASIC or ASSP by the specialized signal Come to remedy. However, FPGA relies on high-level flexibility and promotion of performance and improvement of consumption in the past few years, especially adopt the introduction of high-performance FPGA of 65nm craft in the time in the past two years, subdivide the speed that the market permeates after accelerating one’s own signal that can’t be covered to this DSP. I take Virtex 5 of Xilinx as examples to explain.

6 input LUT ExpressFabric technology that series Virtex-5 adopted was promoted 2 speed ranks of performance to make the dynamic consumption reduce by 35% at the same time, the area shrinks by 45%, the total logic unit counts and reaches 330,000 more. Meanwhile, Virtex 5 high flexible embedding type Block RAM up to 11.6 Mbit, can run with the high working speed up to 550 MHz. Each Block RAM module can store 36 Kbit data at most, can dispose into operating frequency and does not need to consume logic resources for FIFO of 550 MHz, or dispose it for double end mouth RAM in order to increase the bandwidth, the all right grade of antithetical couplets increases and realizes the bigger memory.

In order to meet the need that a designer accelerates to many passways, high-performance DSP algorithm, all series Virtex-5 offer and strengthen the embedded type DSP48E slice piece in a large amount, realize 48 the whole precision results and not need to consume the structural resources of logic in larger dynamic range; The addition chain structure that DSP48E Slice supported special wiring to realize has broken through the performance bottleneck of the addition tree. Does Slice especially on SXT platform facing signals and dealing with reach 6 more? 0, can work in 550 MHz, realize the performance of 352 GMACS. The turning rate of each DSP48E Slice is under 38% of the situations at the same time, the consumption is only 1.38 mW/100 MHz, reduced 40% compared with 90nm deviced.

Higher I/O speed, support more I/O standards

Though the modern electronic system interconnection tends to the exchanging interference network seriallies more and more, divide to difference or single-end walk abreast I/O have increasingly high performance require even. The intersection of MIMO and technology that adopt might need the intersection of system and FPGA with 4 the intersection of 125 MSPs ADC and the intersection of chip and interconnection, 14bit of passway, that serial LVDS export, Company of TI, in the system such as the intersection of LTE and communication, single to divide, might up to 1.04Gbps to supreme the intersection of data and rate while being poor, put forward very high requirement to FPGA; Adopt high clock speed memories such as DDR2, DDR3, QDR2,etc. to realize in the communication system that deal with high-speed signal and buffer memory of the data of dividing into groups in a large amount, also need FPGA to offer the effective connection mouth each other.

The reliable synchronous data of source are gathered to construct the most crucial, difficult challenge that high performance faces while running side by side in the interface, need to deal carefully with noise and bunch among Skew and signal of the clock, data space to disturb. If a device can be realized: 1.25 The difference of Gbps divides I/O or 800 Mbps form end I/O interconnection; Can support the high-performance I/O standard agreement of 40 multi-type and customize electric standard agreement within the range of wide voltage, speed; Can guarantee the clock aligns ShiXu to require with the data, simplify the source sync cap to design, make sure easily in or memory interface the high energy runs side by side synchronously, it will be very ideal. Virtex 5 of Xilinx is passing and utilizing the enhanced SelectIO piece, ChipSync technology and Sparse chevron encapsulate technology, earthing in charge of distribution method of foot realize the above-mentioned index of performance: Guaranteeing the clock lies in the middle of valid window of data, realize that can need, also meet communication, signal dealing with, figure, stores, network exchanging and need on I/O device of new generation, and will design the risk to minimize, save the investment in ASSP and ASIC in early days.

Lower consumption Low cost

Xilinx, through adopting new craft, new technology to series Virtex-5, encapsulating newly and integrating hard IP etc. in a large amount, make engineer use the intersection of 65nm and the intersection of craft and FPGA go on, design, can reduce, design, reduce the consumption and promote systematic function at the same time notably while in risk by a wide margin, realize the best equilibrium of the performance and consumption, and promote and design the speed. This includes: Adopt ExpressFabric simultaneous to enable the dynamic consumption lower by 35% in whom technology promote performance 30%; Utilize 65nm three grid to oxidize one layer of technology to reduce in order to leak the electric current as the static consumption of the main fact; Adopt the new RocketIO GTP transceiver, make the consumption reduce 77% compared with previous generation’s device; Smaller heat-dissipating system further reduces the systematic consumption; Imbedded formula Block RAM and has been distributed formula RAM/FIFO and reduced the demand for the outside RAM; ChipSync circuit can adjust the clock to the centre of data, thus guarantee the dependability of the interface of the memory; SelectIO circuit can be flexible to support I/O interface standard on various sheets; DSP48E slices has offered available addition device and accumulating device for embedded multiplier; RocketIO GTP transceiver offers built-in bunch I/O performance and the lowest consumption in the industry of walking; PCI Express extreme point module is designed to use with RocketIO GTP transceiver, in order to offer and used in compatible PCIe to connect the function; 10/100/1000 Ether network MAC module uses with RocketIO GTP transceiver, offers built-in Ethernet to connect the above advantages based on 65nm craft device of the function, have reduced the comprehensive cost of system greatly, for example realize PCI Express of x8 mode, Virtex-5 FPGA which uses Xilinx can save nearly 10,000 LUTs more than the same grade device of other manufacturers.

In addition, the unique tube foot that Sparse chevron of Virtex-5 encapsulates technology arranges and disturbs and improves the signal integrality after reducing bunch, contribute to removing board one grade of debugging and heavy design processes with high cost. The electric capacity of bypass of substrate removes several hundred pieces of external electric capacity, can simplify PCB overall arrangement and connect up, narrow PCB size, make the systematic cost reduce again.

If the consumption of FPGA reaches certain scale, can also use 65nm EasyPath technology of Xilinx, reduce the production cost of the batch by 30-75% while guaranteeing the device quality, and shorten time of delivery by a wide margin.

Embodiment and conclusion

As far back as February of 2006, companies such as Mercury Computer Systems, VMETRO,etc. have already begun to use * to estimate Virtex-5 series FPGA actually, and * estimates the result and impels more manufacturers to turn to Virtex-5 FPGA of 65nm rapidly.

Benefit from the logic and memory capacity oversize of series Virtex-5 LX, the intersection of DN9000K10PCIe and board of DiNI adopt 6 Virtex-5 LX330 and 1 LX50T can realize up to 11 million doors of grade the intersection of ASIC and task of proving. Nallatech and Alpha Data adopt LX110T to realize high-performance PMC calculates the sub board. VMETRO adopts Virtex-5 LX110T to realize the interface of high-performance CPCI and deal with the module, adopts V5LX110T and V5SX95T to realize that deals with the platform in high-performance VXS signal. Curtiss-Wright regards LX330T as the core to construct CHAMP-FX2 high-performance signal and deal with the platform. Sundance adopts Virtex-5 LXT or SXT to construct the flexible embedded treatment module.

65nm craft FPGA already nibbled the traditional markets of ASIC and ASSP progressively, a great deal of high-performance fields of applying to network, telecommunication, storing, server, calculation, wireless, broadcast, video, formation of image, medical treatment, industry and military extensively etc., especially become the ideal system integration platform on the advanced market represented by many model’s wireless base stations.